Adaptive Verification IP
From WikiCover
On June 4, 2007, ARM announced at the 44th Design Automation Conference in San Diego, California, the AMBA Adaptive Verification IP, a unique technology that for the first time conquers the increasingly complex challenge of verifying entire on-chip communication systems. Adaptive Verification IP enhances existing SoC verification methodologies, via the industry's only engine for extracting and applying traffic profile information to predict how systems will perform.
Adaptive Verification IP combines the time-to-market advantages of automated verification with the quality of in-context, knowledge-based verification that was previously only possible manually. Adaptive Verification IP complements existing random or directed-random methods with a powerful new approach to reducing overall verification time, improving verification confidence, and enabling the explosion in SoC size and complexity to continue.
As the design cycle increasingly begins at the system level, so must verification. For high-level modeling, Adaptive Verification IP can be licensed as an add-on to the RealView SoC Designer tool, which provides a system-level framework that architects of today's most complex SoCs use to create, explore and optimize platforms long before the hardware and software teams begin their work.
Adaptive Verification IP is written C++ and encapsulated in System Verilog for RTL compatibility. To provide a detailed verification of system functionality and performance, Adaptive Verification IP can also be licensed standalone for use within all popular verification tool flows from the leading EDA vendors.
Mentor Graphics is the first major EDA vendor to ensure that Adaptive Verification IP functions smoothly within its verification methodology.