Synopsys DesignWare
From WikiCover
On June 27, 2007, Synopsys announced that it has teamed with UMC to port the Synopsys DesignWare USB 2.0, PCI Express, SATA and XAUI PHY semiconductor intellectual property (IP) to UMC's 90-nanometer (nm) and 65-nm technologies. The DesignWare PHYs are highly complex, process-tuned analog interfaces used in today's high-volume, high-value consumer, computer, storage and networking SoCs. The DesignWare PHY IP provides 90- and 65-nm implementations of popular high-speed derail communications protocols, helping reduce risk, speeding time-to-market, and ensuring a more predictable path to silicon success.
The USB 2.0 nanoPHY for USB 2.0 is a mixed-signal IP core that is ideal for USB applications that require low power, small area, and PHY tunability. Combined with the DesignWare USB Device, Host and On-The-Go controllers and verification IP, Synopsys' DesignWare USB IP provides designers with an easy-to-integrate, interoperable USB IP solution that can be quickly implemented into next-generation applications.
The DesignWare PHY IP for PCIe, XAUI, and SATA, combined with the respective DesignWare digital controllers and verification IP, delivers a complete set of IP solutions for these protocols. The PHY IP offers the lowest power (30 to 50 percent lower than competitive solutions), high performance margins, and small die area. In addition, the ATE test vectors and a unique built-in diagnostic engine enable at-speed production testing of the mixed-signal PHYs. The associated DesignWare verification IP enables a quick and efficient way to verify PCI Express designs using the latest functional verification methodologies.
The DesignWare USB 2.0 nanoPHY for UMC's 90LL, 65-nm SP, and 65LL processes are expected to be available in the second half of this year. The DesignWare PHY IP for PCI Express, XAUI and SATA implemented in UMC's 90LL and 65-nm SP technologies are expected to be available in early 2008. The DesignWare verification IP and digital controller cores for USB 2.0, PCIe and SATA are available today.
Synopsys enables designers to quickly integrate analog mixed-signal IP (MSIP) into next-generation SoCs by offering a comprehensive portfolio of high performance PHY IP for PCI Express, SATA, XAUI, USB, and DDR2/DDR3 protocols and associated digital controllers and verification IP. The MSIP offering also includes a comprehensive suite of I/O libraries. Available for industry-leading processes, the DesignWare Mixed Signal IP portfolio meets the needs of today's high-speed SoC designs for the networking, storage, computing, and consumer electronics markets.